1. Field of the Invention
The present invention relates to high-voltage semiconductor devices using an SOI (silicon on insulator) substrate, the devices being mainly intended for use in a power conversion integrated circuit represented by an HVIC (high voltage integrated circuit). The devices can be used for an LDMOSFET (lateral double diffused MOSFET) of a high withstand voltage class in the range of 100 V to 1,200 V.
2. Description of the Related Art
Recently, with a demand for high withstand voltage of a power IC containing a high withstand voltage element, SOI substrates are attracting attention, which allow complete isolation between elements by trench dielectric isolation and dielectric insulation layers. A high withstand voltage power conversion integrated circuit formed on an SOI substrate has advantages of preventing malfunction due to a parasitic element upon a switching process and interference due to a noise, and reduction of parasitic capacitance. Since the dielectric isolation by trenches can be applied to an edge structure and a high voltage junction termination (HVJT) structure of the devices in the integrated circuit, an effect of chip size shrink of the integrated circuit itself can also be expected.
FIGS. 11(a) and 11(b) are circuit diagrams of an example using a conventional HVIC. FIG. 11(a) is a circuit diagram of a resonance type half bridge power supply, and FIG. 11(b) is a block diagram showing an internal construction of the HVIC of FIG. 11(a). As shown in FIG. 11(a), the conventional resonance type half bridge power supply comprises an HVIC 150, output terminals of which are connected to MOSFETs 11 and 12 with wirings. The HVIC 150 gives driving signals to the MOSFETs 11 and 12 to drive the MOSFETs 11 and 12.
A drain terminal of the high potential side MOSFET 11 in FIG. 11(a) is connected to a first wiring 33. The first wiring 33 is subjected to a high dc voltage of from 400 V to 500 V. A source terminal of the low potential side MOSFET 22 is connected to the ground (referred to as a “GND” in the following description). A source terminal of the high potential side MOSFET 11 and a drain terminal of the low potential side MOSFET 22 are connected by a second wiring 44. A bootstrap circuit is constructed by a bootstrap diode 55 and a capacitor 66 and is a power source for a floating reference gate drive circuit 23 of the HVIC 150 of FIG. 11(b).
An electric potential of the wiring 44 varies between GND and Vdd corresponding to switching operation of the MOSFET 11 and the MOSFET 22, in which Vdd is an electric potential of the high potential side of the high voltage power supply of FIG. 11(a) and GND is an electric potential of the low potential side. Therefore, a floating reference gate drive circuit must be provided in order to drive the high potential side MOSFET 11, the floating reference gate drive circuit driving the gate of the MOSFET 11 on a base potential that varies between GND and Vdd. In addition, a level shift circuit 24 must be provided between the floating reference gate drive circuit and a control circuit of a low potential base circuit (a GND base circuit) with a base potential of the GND level. Thus, the HVIC 150 provided with a floating reference gate drive circuit 23 and a level shift circuit 24 has been proposed.
As shown in FIG. 11(b), the HVIC 150 comprises a control circuit 21, a driving circuit 25, the floating reference gate drive circuit 23, and the level shift circuit 24. The output terminals of the floating reference gate drive circuit 23 and the driving circuit 25 each having a gate driving circuit are electrically connected to gate electrodes of the high potential side MOSFET 11 and the low potential side MOSFET 22, respectively, with a wiring. The control circuit 21 and the driving circuit 25 are GND base circuits 27 with a base potential of the GND.
The control circuit 21 generates control signals for turning the MOSFETs 11 and 12 ON/OFF (the signals being referred to as ON/OFF signals). The control circuit 21 receives an alarm signal and a warning signal from the floating reference gate drive circuit 23.
The floating reference gate drive circuit 23 gives a driving signal to the gate terminal of the high potential side MOSFET 11 connecting to the Vdd side and operates based on a potential of an output voltage that varies according to switching of the MOSFET. The floating reference gate drive circuit 23 receives an ON/OFF signal for the MOSFET generated by the control circuit 21 and raised by the level shift circuit 24, and turns the high potential side MOSFET 11 ON/OFF according to the received ON/OFF signal.
The floating reference gate drive circuit 23 further has functions of temperature detection, overcurrent protection, and low voltage protection, and turns the high potential side MOSFET 11 OFF according to the detected information. An alarm signal and a warning signal based on the detected information are, after level reduction by the level shift circuit 24, sent to the control circuit 21.
The driving circuit 25 receives an ON/OFF signal for the low potential side MOSFET 22 generated by the control circuit 21 and turns the MOSFET 22 ON/OFF according to the received ON/OFF signal.
The level shift circuit 24 transforms the ON/OFF signal for the MOSFET 11 generated by the control circuit 21 from signal with a GND base level to a signal with a floating reference level higher than the GND level. The level shift circuit 24 outputs the transformed signal to the floating reference gate drive circuit 23.
The level shift circuit 24 comprises, for raising the base level, a high withstand voltage NMOSFET and a level shift resistor connecting to a drain terminal of the high withstand voltage NMOSFET. The level shift circuit 24 also comprises, for reducing the base level, a high withstand voltage PMOSFET and a level shift resistor connecting to a drain terminal of the high withstand voltage PMOSFET. The level shift circuit 24 can have a construction functioning solely for raising the base level.
The HVIC 150 of FIG. 11(b) is formed by integrating the control circuit 21, the floating reference gate drive circuit 23, the level shift circuit 24, and the driving circuit 25 whole on a single semiconductor substrate. There can be other cases, in one of which only the level shift circuit 24 and the floating reference gate drive circuit 23 are integrated on the same semiconductor substrate. In another case, the MOSFET 11 and the MOSFET 22 are also integrated on the same semiconductor substrate that has the HVIC 150.
FIG. 16 is a sectional view of an essential part of a conventional high-voltage semiconductor device. The conventional high withstand voltage semiconductor device 950 of FIG. 16 can be used for a high withstand voltage NMOSFET for raising the base level in the level shift circuit 24 of FIG. 11(b).
The high-voltage semiconductor device 950 comprises a support substrate 900, a dielectric layer 901 provided on the support substrate 900, and a semiconductor substrate of an n− type semiconductor layer 902 provided on the dielectric layer 901. The dielectric layer 901 performs dielectric isolation between the support substrate 900 and the n− type semiconductor layer 902. Lateral dielectric isolation in the n− type semiconductor layer 902 is accomplished by trench dielectric isolation carried out by a silicon oxide film 904 embedded in a trench 903 formed in the n− type semiconductor layer 902. The trench dielectric isolation partitions the n− type semiconductor layer 902. In a predetermined region of the partitioned n− type semiconductor layer 902, which functions as a drift drain region 902, formed are: a high concentration drain n+ layer 913 and an n type buffer layer 912 with higher resistivity than that of the drain n+ layer 913 disposed at the center in the upper surface region of the drift drain region 902; and a p type well diffusion layer 911 separated from and surrounding the n type buffer layer 912 and a source n+ layer 914 in the p type well diffusion layer 911. A gate electrode 910 is provided over the source n+ layer 914, the p type well diffusion layer 911, and the drift drain region 902 intercalating an insulation film. The source n+ layer 914 and the drain n+ layer 913 have a source electrode 908 and a drain electrode 909 formed on the respective n+ layers. The source electrode 908 and the drain electrode 909 are insulated from each other by a field oxide film 905, an interlayer dielectric film (an ILD film) 906, and a passivation film 907.
The source electrode 908 for the source n+ layer 914 and the drain electrode 909 for the drain n+ layer 913 are extending from one another over the drift drain region 902 to form a field plate electrode.
When the support substrate 900, the source electrode 908, and the gate electrode 910 are fixed to the ground potential and a positive bias voltage is applied to the drain electrode 909, a depletion layer expands from a pn junction between the p type well diffusion layer 911 and the n− type semiconductor layer 902 of the semiconductor device 950. At the same time, a depletion layer also expands from an interface between the dielectric layer 901 and the n− type semiconductor layer 902 because the support substrate 900 is fixed to the ground potential. The both lateral and vertical expansion of depletion layer in the n− type semiconductor layer 902 mitigates the surface electric field in the drift drain region 902.
This effect is generally called a RESURF effect (a reduced surface field effect).
Design of the high-voltage semiconductor device 950 is conducted so that the surface electric field is mitigated, electric field concentration at the pn junction is restrained, and avalanche breakdown at the semiconductor substrate surface is avoided even on application of high voltage on the drain electrode 909, by means of taking a sufficiently long distance Ld between the n type buffer layer 912 and the p type well diffusion layer 911 in the drift drain region 902, adjusting an impurity concentration optimum, and optimizing the length of extension of the field plate electrode.
In this condition, an avalanche breakdown takes place at the interface between the drift drain region 902 and the dielectric layer 901. A breakdown voltage Vbr of a high-voltage semiconductor device that fulfills the RESURF condition is represented by the following formula obtained by transforming Poisson equation.[Mathematical Formula 1]Vbr=Ecr×(d/2+Tox×∈si/∈ox)  (1)in which Ecr is a critical electric field, d is a thickness of the n− semiconductor layer 902 (in μm), and Tox is a thickness of the dielectric layer 901 (in μm). In the case the n− type semiconductor layer 902 is formed of silicon and the dielectric layer 901 is formed of a silicon oxide film, the breakdown voltage Vbr is 750 V taking specific values of Ecr=3E5 V/cm, d=20 μm, Tox=5 μm, ∈Si=11.7, and ∈ox=3.9.
A breakdown voltage generally required by a level shifter and a bootstrap diode mounted on an HVIC is at least 750 V in a product specification of 600 V rating, considering a main power supply voltage Vdd of a high voltage of 400 V, scattering of resistivity of the n-type semiconductor layer 902, scattering of thickness in processing the dielectric layer 901, and further, requirement for the breakdown voltage of the level sifter and the bootstrap diode that must be equivalent or higher than an actual breakdown voltage of the power MOSFET or an IGBG to be controlled by the HVIC. For an HVIC of an 800 V rating, which is used in driving a motor or an inverter, a main power supply voltage Vdd is a higher voltage of about 500 V. As a result, a level shifter of a high withstand voltage NMOSFET 950 that is a level shifter, needs a source-drain withstand voltage of about 1,000 V.
The Mathematical Formula 1 indicates that a high withstand voltage of a high-voltage semiconductor device can be attained by increasing the thickness d of the n− type semiconductor layer 902 or the thickness Tox of the dielectric layer 901. The thickness d of the n-type semiconductor layer 902 has restrictions in the manufacturing processes including etching and oxidation film-embedding in the trench for laterally partitioning function elements on the n− type semiconductor layer 902. Therefore, a practical thickness d is in the range of 10 to 20 μm. The thickness Tox of the dielectric layer 901 also has a problem of rise of an SOI substrate cost because of a problem of large warp of the wafer in the IC production process for a thick SOI substrate with a laminated construction and because of increase in deposition time of dielectric layer 901 using a high temperature furnace. In addition, a thick dielectric layer 901 diminishes expansion of a depletion layer from the junction between the dielectric layer 901 and the n− type semiconductor layer 902, decreasing the RESURF effect. Thus, an electric field on the surface of the high-voltage semiconductor device becomes severe and the withstand voltage decreases. Consequently, reality in mass production is lost in an SOI substrate with a dielectric layer composed of a silicon oxide film having a thickness not smaller than Tox=6 μm, in consideration of a withstand voltage, a substrate cost, and wafer warping.
As a consequence, in order to meet the high withstand voltage requirement by industrial and on-vehicle HVICs of a 800 V class rating voltage, it is still difficult, only by optimizing a thickness of the embedded dielectric layer (the dielectric layer 901) and a thickness and an impurity concentration of the n− type semiconductor layer 902, to attain an aimed withstand voltage, to say nothing of developing market products.
In constructing a power conversion integrated circuit such as an HVIC, high voltage wiring connection is done with an aluminum wiring or a bonding wire from a drain electrode of a high withstand voltage NMOSFET functioning as a level shifter element to a floating reference gate drive circuit region (an HV island) having a dielectrically isolated high side driving circuit. The high voltage wiring connection is carried out form a dielectrically isolated high withstand voltage NMOSFET to an adjacent or a separated floating reference gate drive circuit region stably without creating a local withstand voltage-limiting region. Japanese Unexamined Patent Application Publication No. 2006-313828 (hereinafter “Patent Document 1”) and Japanese Patent No. 4020195 (hereinafter “Patent Document 2”) disclose a method of high voltage wiring connection with a bonding wire. Patent Documents 1 and 2 disclose a technique to maintain a high withstand voltage of a semiconductor device by disposing another dielectric layer adjacent to the original dielectric layer in the lamination direction.
As described above, in order to attain HVICs for industrial and on-vehicle applications of voltage ratings of 600 V and 800 V using an SOI substrate, there are two main problems in obtaining commercial products; to achieve a high withstand voltage in the level shifter element of a high withstand voltage NMOSFET and to accomplish high voltage wiring outputted from the drain electrode of the level sifter.
In order to cope with the two problems, Japanese Unexamined Patent Application Publication No. 2006-148058 (hereinafter “Patent Document 3”) discloses a technique using a device comprising a plurality of transistor elements that are level shifter elements dielectrically isolate and connected in series with one another.
FIG. 12 shows a basic equivalent circuit of the semiconductor device disclosed in Patent Document 3. FIG. 13 is a schematic plan view showing arrangement of composing elements indicated in the circuit diagram of FIG. 12. FIG. 14 is a sectional view cut along the line A-A in FIG. 13 and FIG. 15 is a sectional view cut along the line B-B in FIG. 13.
Referring to FIG. 12, n (≧2) transistor elements Tr1 to Trn dielectrically isolated with and from each other are sequentially connected between the GND potential and the predetermined potential Vs with the side of the GND potential being the first stage and the side of the predetermined potential Vs being the n-th stage. The gate terminal of the first stage transistor Tr1 is an input terminal. n resistance elements R1 to Rn are sequentially connected in series between the GND potential and the predetermined potential Vs with the side of the GND potential being the first stage and the side of the predetermined potential Vs being the n-th stage. The gate terminals of the transistor elements Tr2 to Trn are sequentially connected to the connection points between adjacent stages of series connected resistance elements R1 to Rn. An output is extracted from a terminal at the side of the predetermined potential Vs of the n-th stage transistor Trn, through a load resistor (not shown in the figure) having a predetermined resistance value.
A multiple of field isolation trenches T1 to Tn are formed reaching the embedded dielectric layer 3 as shown in FIGS. 13, 14, and 15. Each of the n transistor elements Tr1 to Trn dielectrically isolated with each other is sequentially disposed in each filed region surrounded by each of the field isolation trenches T1 to Tn surrounding and containing higher stage transistor elements. Wiring that crosses over a dielectric isolation trenches 4 and Tn is formed with a metal wire.
However, in the structure of transistors as shown in FIG. 13 and FIG. 14 in the construction disclosed in Patent Document 3, a metal wire crossing over the trench is used for a high voltage wiring connecting the drain of the Tr n−1 to the source of the Trn, for example. As a consequence, the metal wiring at a high voltage may cause dielectric breakdown of the interlayer dielectric film under the metal wiring. In addition, the metal wiring at a high electric potential level increases a leakage current from the metal wiring of the drain along an inner wall of a dielectric isolation trench to the source region surrounded by the same isolation trench. Therefore, means must be taken to prevent the interlayer dielectric film from dielectric breakdown, to suppress leakage current, and to reduce a voltage born by each transistor element. As a result, a multiple stage series connection of 5 to 6 stages is required for obtaining a withstand voltage of 1,000 V.
In such a multiple stage construction of 5 to 6 stages, at the time of start up of the HVIC, in which a low side transistor of externally arranged power transistors (MOSFETs or IGBTs) turns ON and a Vs voltage in the floating reference gate drive circuit region of the HVIC becomes the GND potential, the ON resistance of the level shifter is ON resistance per one transistor element (1 kΩ, for example) times 5 to 6 (the number of transistors). Provided an ON current being 1 mA, the ON voltage of the level shifter amounts to 1 kΩ×1 mA×(5-6)=5-6 V, which is a problematically large value. A high ON voltage of the level shifter requires raising a lower limit voltage of a low input under voltage lock out circuit (UVLO circuit) contained in a high side driving circuit. The UVLO circuit halts a circuit operation of the floating reference gate drive circuit region when an electric potential at a high potential side terminal of the floating reference gate drive circuit region power supply decreases to a value lower than a predetermined potential. As a consequence, a problem arises that an operation voltage range of the floating reference gate drive circuit region circuit is narrowed since low voltage operation is restricted corresponding to the elevated lower limit voltage of the ULVO circuit.
Due to the multiple stage series connection construction of the MOSFETs, each of the multiple stage connected MOSFETs has, in observation from the first stage MOSFET, cumulated amount of n parallel connected stages of gate-source capacitance component Cgs, a gate-drain capacitance component Cgd, and further, a source-drain junction capacitance Cds. Consequently, the RC time constant increases and degrades the response performance in high speed switching operation.